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[Embeded-SCM Develop] ref-ddr-sdram-vhdl.zip

Description:
Platform: | Size: 1031343 | Author: | Hits:

[Other resource] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[Other resource] t26a_ibis

Description: ddr sdram 的控制代码，采用VHDL语言书写
Platform: | Size: 282097 | Author: zxb | Hits:

[Other] mem-ctrl-rtl

Description: 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
Platform: | Size: 44032 | Author: zz | Hits:

[Other Embeded program] ddr_sdram_controller

Description: DDR SDRAM Controller design
Platform: | Size: 2400256 | Author: Jerry | Hits:

[Software Engineering] TheResearchoftherealtimesignalprocessingofSARbased

Description: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given
Platform: | Size: 5155840 | Author: mabeibei | Hits:

[Software Engineering] SDRAM

Description: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Platform: | Size: 1903616 | Author: luyi | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_MT46V32M16TG

Description: ddr控制器 对DDR实现读写控制-ddr control
Platform: | Size: 548864 | Author: 张琦 | Hits:

[VHDL-FPGA-Verilog] DDR

Description: HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Platform: | Size: 3968000 | Author: 网络蚂蚁 | Hits:

[VHDL-FPGA-Verilog] ddr_code

Description: 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware description language
Platform: | Size: 11264 | Author: 阳阳 | Hits:

[VHDL-FPGA-Verilog] DX-PHY

Description: ddr phy design spec and example-ddr phy design spec and example!!
Platform: | Size: 250880 | Author: yangxf | Hits:

[Software Engineering] ddr_sdr_V1_1

Description: its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
Platform: | Size: 37888 | Author: james | Hits:

[VHDL-FPGA-Verilog] sdram_controller_latest.tar

Description: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Platform: | Size: 30720 | Author: Andrei | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Platform: | Size: 8483840 | Author: 熊熊 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMconclude

Description: DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some reference
Platform: | Size: 2262016 | Author: 董萌 | Hits:

[VHDL-FPGA-Verilog] emb-dev-c3-appsel

Description: vhdl code for altera ddr design
Platform: | Size: 4072448 | Author: clement | Hits:

[VHDL-FPGA-Verilog] model

Description: 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
Platform: | Size: 7168 | Author: momowang | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[Windows Develop] treff-ddr-sdrh

Description: 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
Platform: | Size: 439296 | Author: wyq52103 | Hits:

[VHDL-FPGA-Verilog] ddr_sdram

Description: 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
Platform: | Size: 20480 | Author: 唛侬 | Hits:
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